Why doesn’t the F-Tile Debug Toolkit in the F-Tile Avalon® Streaming IP for PCI Express* report error work in the Quartus® Prime Pro Edition Software v21.4 ?
Description Due to problems in the F-Tile Debug Toolkit in the Quartus® Prime Pro Edition Software v21.4, the F-Tile Debug Toolkit does not run when F-Tile is configured in 1 x4 endpoint mode. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. A patch is available to fix this problem for the Quartus Prime Pro Edition Software version 21.4. Download and install Patch 0.19 below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 22.1.Why does the GTS JESD204B IP Design Example in Dual Simplex PHY only mode remain in the reset state when simulating with the VCSMX simulation tool?
Description Due to a problem in the 24.3.1 release of the Quartus® Prime Pro Edition software, the tx_out_of_reset output port is unconnected in the GTS JESD204B IP Design Example in Dual Simplex PHY only mode. This error causes the system to be unable to release both the link reset and frame reset. As the IP is in reset, the IP simulation fails to start. Resolution To work around this problem in version 24.3.1 of the Quartus® Prime Pro Edition software, connect u_jesd_gts_ed_qsys_RX_TX|jesd_gts_ss_rx_tx|ds_group_jesd204b|tx_phy_ds_group_0_inst0_auto_jesd204_tx_out_of_reset (export output port to top level) to wire named tx_out_of_reset[0] in top level wrapper (intel_jesd204b_gts_ed_RX_TX.sv) Additionally, Altera recommends installing the patch in the Quartus® Prime Pro Edition Software version 24.3.1. After installing the patch, regenerate the GTS JESD204B IP Design Example and run the simulation. This problem is fixed in version 25.1 of the Quartus® Prime Pro Edition Software.Why does the F-tile Serial Lite IV IP Design Example fail?
Description Due to a problem in the Clock Controller GUI of the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit, the F-tile Serial Lite IV IP Design Example fails when you need to configure the OUT1 clock frequency of the chip Si5332. This is because there is a problem with this Si5332 GUI; the OUT1 frequency can not be accurately configured. Similar failures might be seen for all Agilex™ 7 F-tile IP designs if you use the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit, your design utilizes the Si5332 OUT1 clock, and the default frequency, 166.66 MHz, needs to be changed. Resolution To work around this problem, you should avoid setting the Si5332 OUT1 frequency directly using the "set" button. You need to use the "import" button to accurately set the Si5332 OUT1 clock frequency. ClockBuilder Pro software can export the import function of a TXT file. A sample si5332 project and a si5332-project.txt file are attached for reference. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Which Fast Simulation Macros are documented for the Agilex™ 7 FPGA F-Tile Hard IP?
Description This KDB details the recent advancements in macro development to improve simulation speeds for the Agilex™ 7 FPGA F-Tile Ethernet IPs. Its purpose is to clarify the specific macros applicable to various IPs and their compatibility with different versions of the Quartus® Prime Pro Edition Software. Other Macros already detailed in existing documentation, ip scripts or design examples should continue to be used as is. In any other circumstance, you should not pro-actively add them to your design. Resolution Refer to the attached document. This document provides an extensive overview, showing the macros applicable to each IP. This will help you quickly identify the appropriate macro for your simulation needs.Why isn't the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Stratix® 10 FPGA IP compliant to the PCS transmit code group-state diagram written in the IEEE 802.3 Clause 36 when sending /I2/ Ordered Set?
Description Due to a problem in the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Stratix® 10 FPGA IP, you might see the incorrect running disparity /I2/ Ordered Set in 1GbE mode. According to the IEEE 802.3 Clause 36, /I2/ Ordered Set should be /K28.5-/D16.2+/ during IDLE duration. However, the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Stratix® 10 FPGA IP may generate an inverted running disparity of /I2/ Ordered Set which is /K28.5+/D16.2-/. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 21.2. Download and install Patch 0.45 below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 22.3.Why are the configuration pin names in the Quartus® Prime Pro Edition Software v21.2 different to the User Guides and Pin Connection Guidelines?
Description Due to a problem in the Quartus® Prime Pro Edition Software v21.2, you will see SDMMC_CFG* pin names instead of AS_nRST and PWRMGT_ALERT pin names when targeting the following Agilex™ 7 FPGA F-Series devices: AGFA014/AGFB014 (R24A) AGFA012/AGFB012 (R24A) AGFA022/AGFB022 (R25A) AGFA027/AGFB027 (R25A) You will see that the following documentation have replaced the SDMMC_CFG* pin names with AS_nRST and PWRMGT_ALERT pin names for Agilex™ FPGA F-Series devices: Agilex™ 7 FPGA Configuration User Guide Agilex™ FPGA Power Management User Guide Agilex™ 7 FPGA Device Family Pin Connection Guidelines Agilex™ FPGA Device Pin-Out Files Resolution A patch 0.27 is available to fix this problem for the Quartus® Prime Pro Edition Software v21.2. Please download and install the patch below. This problem is fixed starting with the Quartus® Prime Pro Edition Software v21.3.
Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz.
Description You may see the following error when entering 805.664062 MHz into the GTS System PLL Clocks IP "Output frequency C0" field, to match the frequency requirement in the GTS Ethernet Hard IP when configured for 25G-1 Ethernet on Agilex TM 5 FPGA devices using the Quartus® Prime Pro software version 25.3.1 and earlier. Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz. Error: <filename>.intel_systemclk_gts_0: "Refclk frequency" (refclk_xcvr_freq_mhz_0) "156.250000" is out of range: "33.109482", "44.145976", "57.547433", "66.218964", "88.291952", "99.328446", "110.364940", "115.094866", "132.437928", "154.510916", "165.547410", "172.642299", "176.583904", "198.656892", "220.729880", "230.189732", "231.766374", "242.802868", "264.875856", "286.948844", "287.737165", "297.985338", "309.021832", "331.094820", "345.284598", "353.167808", "364.204302" This problem is caused by the truncated display of the System PLL frequency in the GTS Ethernet Hard IP. Resolution To work around this problem you can enter 805.6640625 MHz into the “Output frequency C0" field of the GTS System PLL Clocks IP. This problem may be fixed in a future version of the Quartus® Prime Pro software.Why does an error occur when upgrading Ethernet designs that use F‑Tile Ethernet Hard IP from Quartus® Prime Pro Edition version 22.4 or earlier to version 25.3.1?
Description Due to an issue in Quartus® Prime Pro Edition software version 22.4 and earlier, an error may be encountered when upgrading Ethernet designs created with F‑Tile Ethernet Hard IP to version 25.3.1. Error: ex_100G.eth_f_0: "Custom Ethernet line rate" (CUSTOM_RATE_GUI) 25.78125 is out of range: 10.3125-17.4 This problem is observed because the maximum supported line rate for the “Custom Ethernet line rate” was incorrectly changed to 17.4 Gbps. Resolution One workaround using the F‑Tile Ethernet Hard IP GUI is to open the .ip file, change the Ethernet mode to a different data rate, and then reconfigure it back to the original data rate. Alternatively, edit the .ip file directly by locating CUSTOM_RATE_GUI and changing its value from 25.78125 to 10.3125 Gbps. This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Warning (19729): Current CMF data structure hash (0xA2C420AC) is older version than latest CMF data structure but still allowable.
Description You may see the warning message above when configuring an Stratix® 10 FPGA device or generating a programming file with the Programming File Generator in Quartus® Prime Pro Edition Software version 19.4. Resolution You can safely ignore this warning. Alternatively, a patch is available to fix this problem for the Quartus Prime Pro Edition Software version 19.4. Download and install Patch 0.29 below.Why does the Stratix® 10 FPGA SmartVID device fail to configure in PMBus Master Mode when using Quartus® Prime Pro Edition Software firmware version 21.3?
Description Due to a problem when using Quartus® Prime Pro Edition Software versions 21.1, 21.2, and 21.3 and Stratix® 10 FPGA SmartVID devices with a VID fuse value of 900mV, there is a missing VOUT_COMMAND in PMBus Master Mode. This causes the external voltage regulator to not be configured to the expected voltage level resulting in configuration failure. Resolution To work around this problem, use the patch for Quartus® Prime Pro Edition Software version 21.3 below. For earlier versions of Quartus® Prime Pro Edition Software, contact Altera. This problem is fixed starting from Quartus® Prime Pro Edition Software version 21.4.
