Why can't Symmetric Cryptographic Accelerator (SCA) support be enabled on Agilex® 7 NL[HZ3.1] OPN Devices with AGIC, AGID, AGFC, or AGFD Prefixes in Quartus® Prime Pro Edition Software Version 26.1.1?
Description Agilex® 7 NL OPN devices with prefixes of AGIC, AGID, AGFC, AGFD containing Hard Crypto Blocks (also referred to as the Symmetric Cryptographic Accelerator or SCA) are not supported by Quartus Prime Pro Edition Software version 26.1.1. Although the affected NL OPN devices contain SCA hardware, the Quartus® Prime Pro Edition software version 26.1.1 does not allow users to enable or use the SCA functionality on these devices. This is a restriction in Quartus Prime Pro Edition software version 26.1.1 as the SCA enablement was not completed for NL OPNs. Resolution A general workaround is not available in the Quartus Prime Pro Edition software version 26.1.1. Users requiring SCA support on affected Agilex® 7 FPGA F-Series, I-Series with prefixes of NL OPN as AGIC, AGID, AGFC, AGFD devices may request a patch through Altera support channels where applicable. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do I see RRESP=2 if ECC is enabled in External Memory Interfaces (EMIF) IP?
Description When ECC is enabled in External Memory Interfaces (EMIF) IP of Agilex® 7 FPGA M-Series, Agilex® 5 FPGA, and Agilex® 3 FPGA devices, you might receive RRESP=2 during data readback if any of the following conditions is true. DDR4 Component: Data size of the first write command to the associated AXI4 address ≠ 256 bits * N DDR5 Component/DDR5 DIMM/LPDDR4/LPDDR5: Data size of the first write command to the associated AXI4 address ≠ (Channel DQ width * 16) * N where N is a positive integer (1, 2, 3, ...). The hard memory controller uses fixed DQ burst length. The above conditions generate partial access to the memory. The uninitialized portion of data in the memory will cause uncorrectable ECC error, leading to RRESP=2. Below are some example scenarios that showcase this RRESP problem. Example #1: When using a x16+ECC DDR4 Component interface in fabric accessing mode, the first write command to an AXI4 address is a partial access with the use of WSTRB. WDATA width = 256 bits, AWLEN = 0, WSTRB = 0x0000FFFF: Data size of the first write command to the associated AXI4 address = 128 bits Example #2: When using a 1chx32 LPDDR5 interface with in-line ECC enabled in fabric accessing mode, the first write command to an AXI4 address has only one WDATA beat. WDATA width = 256 bits, AWLEN = 0: Data size of the first write command to the associated AXI4 address = 256 bits Channel DQ width * 16 = 512 bits Example #3: When using a x32+ECC DDR5 RDIMM interface in 256-bit NoC accessing mode, the first write command to an AXI4 address uses an even number AWLEN value. WDATA width = 256 bits, AWLEN = 2: Data size of the first write command to the associated AXI4 address = 768 bits Channel DQ width * 16 = 512 bits Resolution To work around this problem, ensure the data size of the first write command to the associated AXI4 address equals to either 256 bits * N or (Channel DQ width * 16) * N, depending on the memory protocol. An alternative method is available starting with Quartus® Prime Pro Edition Software version 26.1.1. When IP parameter Initialize Memory in the Advanced Calibration Settings section is enabled, on calibration passing, and before handing off control of the memory to user logic, the memory will be initialized with all zeros in the data section and the corresponding ECC codes in the ECC section. With this approach, there is no special requirement on the data size of the first write command to the associated AXI4 address. Note: To avoid leading to long simulation time, only the first 256 bytes of memory will be initialized in simulation when Initialize Memory is enabled. Additional Information DDR4 DIMM interface and LPDDR5 interface using link ECC are not affected by this RRESP problem.Why do I see this warning message after enabled Transceiver Toolkit Debugging Features in GTS SDI II Serial Loopback Design Example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you will observe below. “warning check failed! > warning: no path is found satisfying assignment" “set_max_skew -from get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|in_wr_ptr_gray -to get_registers auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t1_fifo|write_crosser|sync.u|din_s1 -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 - This assignment will be ignored.” It happens when user enables the Transceiver Toolkit Debugging Features in GTS SDI II Serial Loopback Design Example. This problem happens due to the undefined path of the dc_fifo.sdc. Resolution This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why am I seeing High Severity DA warning: "Multiple Clock Domains Driving a Synchronizer Chain" after enabled Transceiver Toolkit in Dual-Simplex Parallel loopback Design Example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1.1, you may see a DA warning: "Multiple Clock Domains Driving a Synchronizer Chain" in the compilation report for the GTS SDI II Dual-Simplex Parallel Loopback design example when the transceiver toolkit is enabled. Resolution This DA Warning can be ignored in 26.1.1, and this problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Error message received from device : Internal error. (subcode 0x001A, Info 0x00000000, Location 0x0000701D )
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1.1, you might encounter this error while configuring new signed and encrypted Partial Reconfiguration (PR) persona bitstreams. The problem impacts Agilex® 5 FPGA PR designs enabled for Encryption and Authentication. Resolution This problem will be fixed in a future release of Quartus® Prime Pro Edition Software. No fix is planned in Quartus® Prime Pro Edition Software version 26.1.1. If you encounter this problem, file a ticket through Altera Premier Support (APS) system to requuest a software patch.Error(24244): Found an error when generating the IBIS Output File for board analysis. Refer to "<project_directory>/output_files/xxx.log" for more information
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, you mat see this error when using the EDA Netlist Writer to generate an IBIS Model. This problem occurs when the project includes R-tile or P-tile I/O pins. Resolution This problem has been fixed beginning with version 24.3 of the Quartus® Prime Pro Edition Software.Why is the bus ordering reversed in the Technology Map Viewer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see that the bus ordering is reversed in the Technology Map Viewer. This problem occurs when a design contains a Block Design File (BDF) whose output bus is connected to a SystemVerilog HDL packed array from a top-level SystemVerilog HDL module. For example, the expected mapping in the Technology Map Viewer is: inst0 -> Out[0] inst1 -> Out[1] inst2 -> Out[2] inst3 -> Out[3] However, the actual mapping after compilation in the Technology Map Viewer become: inst0 -> Out[3] inst1 -> Out[2] inst2 -> Out[1] inst3 -> Out[0] Resolution To work around this problem, do one of the following: Convert the BDF file to Verilog HDL or VHDL. Open the BDF file in the Quartus® Prime Standard Edition Software. Select File > Create / Update > Create HDL Design File from Current File. Choose Verilog HDL or VHDL. Replace the original BDF module in the Quartus® Prime Pro Edition Software project with the generated HDL file. Explicitly reorder the bits in the top-level SystemVerilog HDL module by using a SystemVerilog HDL streaming operator in the port connection.Why do I get an error when trying the BKPS provisioning flow commads on my Agilex® 5 FPGA device?
Description Due to a problem in Quartus® Prime Pro Edition 26.1.1, the Quartus Programmer may load the incorrect SDM Firmware when executing the BKPS provisioning flow commands shown below on Agilex® 5 FPGA devices enabled for Post-Quantum Cryptography (PQC) secure boot. quartus_pgm -c 1 -m jtag --bkp_options=bkp_options.txt [--bkp_prefetch] [--bkp_puf_activate] [--bkp_set_authority] The incorrect Firmware is loaded at the start of the commad operation and causes it to fail. Resolution Using the Quartus Programmer, manually generate and preload the correct Agilex® 5 SDM firmware for your specific OPN variant before executing the BKPS commands, as shown below. quartus_pfg --helper_image -o helper_device=[YOUR_OPN] -o subtype=PROVISION -o pqc_mode=OFF provision_pq_cs.rbf quartus_pgm -c 1 -m jtag -o "p;provision_pq_cs.rbf" quartus_pgm -c 1 -m jtag --cmd_code=0x1180 --cmd_param=0xF quartus_pgm -c 1 -m jtag -o "p;provision_pq_cs.rbf" Then, when executing the BKPS commands, use the --skip_init option to prevent the Quartus Programmer from reloading the incorrect Agilex® 5 SDM firmware. quartus_pgm -c 1 -m jtag --bkp_options=bkp_options.txt --skip_init [--bkp_prefetch] [--bkp_puf_activate] [--bkp_set_authority] This issue is scheduled to be fixed in future release of Quartus® Prime Pro Edition Software.Why Does the Jam Player Report "Unable to Read IDCODE" or "Unrecognized Device" When Programming an Agilex® 5 or Agilex® 3 FPGA device with a JAM File Generated Using Quartus® Prime Pro Edition Software Earlier Than Version 26.1?
Description When executing a JAM file generated for an Agilex® 5 / Agilex® 3 device, the programming process may fail with an "Unable to read IDCODE" or "Unrecognized device" error. This occurs because the device IDCODE programmed into the JAM file does not match the IDCODE reported by the target device revision. Example errors: Device #1 unable to read IDCODE Unrecognized device Exit code = 6... Unrecognized Device Resolution To work around this problem, use the DO_IGNORE_IDCODE_ERRORS option when executing the JAM file. This option bypasses IDCODE verification and allows the programming process to continue. Jam Player command: quartus_jli -c <cable> -a <action> <jam> -e DO_IGNORE_IDCODE_ERRORS Example: quartus_jli -c 1 -a CONFIGURE demo.jam -e DO_IGNORE_IDCODE_ERRORS Additional Information Note: The DO_IGNORE_IDCODE_ERRORS option is applied at runtime and does not require recompilation of the design, regeneration of the SOF file, or regeneration of the JAM file. Users can simply add the option to the existing command line when executing the JAM file.What is the time taken by the GTS Ethernet Hard IP for Tx and Rx reset release to mission mode?
Description On hardware, the GTS Ethernet Hard IP transitions to mission mode after reset release within the following times, measured from reset de-assertion to the corresponding ready indicators: Transmit (Tx): approximately 4.55 ms, until tx_lane_stable is asserted Receive (Rx): approximately 11.2 ms, until rx_pcs_ready is asserted Resolution The observed delay is expected behavior for the GTS Ethernet Hard IP; no workaround is required. The design should use these ready indicators to determine mission-mode readiness rather than relying on a fixed delay. Simulation times are shorter because of simplified fast simulation models. Additional Information Hardware time differs from simulation due to fast sim models. In simulation, the GTS Ethernet Hard IP enters mission mode after reset release within these times, Transmit (Tx): approximately 1 ms, until tx_lane_stable is asserted Receive (Rx): approximately 1.016 ms, until rx_pcs_ready is asserted